20 lines
367 B
Makefile
20 lines
367 B
Makefile
# include ../../Makefile.inc
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# SOURCES=$(wildcard *.c)
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# SOURCES_COMMANDS=$(wildcard prompt_commands/*.c)
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# OBJECTS=$(SOURCES:.c=.o)
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# OBJECTS_COMMANDS=$(SOURCES_COMMANDS:.c=.o)
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# ALL_OBJECTS= $(OBJECTS) $(OBJECTS_COMMANDS)
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# STATICLIBS=
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# all: $(OBJECTS)
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# %.o:%.c
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# $(GCC) $(GCCFLAGS) -I./include -c $< -o $@
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# clean:
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# rm -rf *.o
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# .PHONY: all clean print
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